1. Field of the Invention
The present invention relates to a method for fabricating a dielectric isolated (DI) integrated circuit (IC) device. It relates more particularly to a method for fabricating an improved DI substrate to remove the inherent drawbacks associated with its fabricating process.
2. Description of the Prior Art
The use of dielectric isolation (DI) instead of pnjunction isolation in the fabrication of IC devices has become progressively widespread for special fields. Due to its reduced parasitic capacitance and very high inter-device breakdown voltage, the DI IC devices are widely used for apparatus where breakdown damage might occur, such as a switching device for a subscriber line interface circuit (SLIC) of an electronic telephone exchanger.
Dielectric isolation is a method for fabricating ICs in which circuit components are isolated by dielectric layers. FIG. 1 is a partial cross-sectional view of a prior art DI semiconductor substrate. There are electrical element regions 7 or "islands", isolated from each other and from a substrate 6 by individual dielectric layers 4, usually a silicon dioxide (SiO.sub.2) layer. The substrate 6 has a thickness sufficient to support the islands, thus, ensuring mechanical strength. The prior art fabrication of a DI wafer begins with preparing a one conductivity type doped single crystal silicon substrate (original silicon substrate), followed by formation of insulating moats 3 on the surface for the islands 7. Subsequently, a dielectric layer, such as SiO.sub.2 layer 4, is formed covering the entire surface of the wafer, over which silicon is deposited by a conventional chemical vapor deposition (CVD) method using a silicon halide-hydrogen reduction process, to form a layer of a predetermined thickness. The deposited silicon layer is grown at a high temperature such as 1100.degree. C. to form a polycrystalline silicon (polysilicon) layer. Then the wafer is inverted and the original single crystal silicon layer is ground to reveal the DI layers 4 for islands 7. Finally, the front surface of the wafer is finished to a non-defect smooth surface and readied for further fabrication of electrical circuits thereon. (The above process can be understood more easily by observing FIG. 1 upside down. FIG. 1 shows a substrate after the above processes are completed.)
Usually, each island 7 accommodates a circuit element such as a transistor and a film resistor. The island contains a one conductivity type single crystal silicon layer where the circuit element is formed. A heavily doped layer 5 is included to reduce the saturation resistance of the collector of a transistor formed in the island 7.
There are substantial problems in the fabrication of the DI substrate. One of them is a "bow" phenomenon which is warpage or curvature of the multi-layer structure of the wafer after the formation of the polysilicon substrate layer 6 onto the dielectric layer covering the original silicon substrate. There is a difference in the coefficient of expansion between single crystal silicon and polysilicon. The polysilicon layer is grown at a high temperature and the wafer is cooled to room temperature, causing stress inside the wafer to cause "bow". Other problems occur when humps or projections of the coarse structure of polysilicon, formed in the peripheral edge of the wafer, are removed mechanically. Broken, tiny pieces of polysilicon cause mechanical damage to the surface of the wafer during the surface grinding process, thus, reducing wafer yield. Furthermore, channels for scribing formed on the DI wafer are covered with the dielectric layer like other island areas. Accordingly, scribing cutters are easily abraded by cutting the hard dielectric layer. The above problems are all associated with the described prior art method for fabricating a DI substrate.